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Place-and-Route in Libero IDE
Place-and-Route in Libero IDE
Make sure required timing and physical constraints files are associated with the place-and-route tool. There should be
multiple timing and physical constraints files available, covering the PCI functions: 33/66 MHz and 32-/64-bit
operation as well as device package combinations.
T_pcitiming32_33_designer.sdc
T_pcitiming32_66_designer.sdc
T_pcitiming64_33_designer.sdc
T_pcitiming64_66_designer.sdc
TM_pcitiming32_33_designer.sdc
TM_pcitiming32_66_designer.sdc
TM_pcitiming64_33_designer.sdc
TM_pcitiming64_66_designer.sdc
M_pcitiming32_33_designer.sdc
M_pcitiming32_66_designer.sdc
M_pcitiming64_33_designer.sdc
M_pcitiming64_66_designer.sdc
M_pci32_pa3e_FG484.pdc
M_pci64_pa3e_FG484.pdc
TM_pci32_pa3e_FG484.pdc
TM_pci64_pa3e_FG484.pdc
T_pci32_pa3e_FG484.pdc
T_pci64_pa3e_FG484.pdc
For Target-only cores, the T_ files should be used; for Master-only cores, the M_ files should be used; and for Target
and Master operation, the TM_ files should be used.
32/64 selects 32- or 64-bit PCI operation.
33/66 selects 33 or 66 MHz PCI operation.
The supplied timing constraints files assume a typical configuration of the core. Some configurations may cause the
timing constraints files to cause an error when loaded by Designer. For example, if the ONCHIP_IDSEL function is
enabled, the IDSEL input is not used and Synthesis will remove the IDSEL input. When this occurs, Designer will
detect an error when it tries to set a timing constraint on the nonexistent IDSEL input. In this case, the timing
constraints on the IDSEL input should be removed from the SDC files.
If there is not a good match for your selected device and package, you should create your own physical constraints files,
following the rules in the “Implementation Hints” section on page 127 .
v4.0
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相关PDF资料
COREU1LL-AR IP MODULE COREU1LL
COREU1PHY-AR IP MODULE COREU1PHY
CORR-8BIT-XM-UT2 SITE LICENSE IP CORRELATOR XP
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CP2-K3567-SR-F COMPACT PCI - MISC
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